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ZSSC3230 bảng dữ liệu(PDF) 21 Page - Renesas Technology Corp |
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ZSSC3230 bảng dữ liệu(HTML) 21 Page - Renesas Technology Corp |
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21 / 39 page ![]() ZSSC3230 Datasheet © 2019 Integrated Device Technology, Inc. 21 October 15, 2019 Table 8. Analog Output Performance by External Capacitor Value Filter Capacitance (nF) Vout Ripple (µV/V) 0 to 90%Settling Time (ms) Analog Output Resolution (Bit) 100 1000.0 2.3 10 400 250 9.2 12 1600 62 36.8 14 6400 16 147.2 16 Figure 13. PDM Output Configuration C0 CC CC ZSSC3230 VDD VSS RESQ PDM VSS VDD AOUT 6.6.2 I2C Output The ZSSC3230 supports an I2C slave interface for digital output operation. The implementation of the interfaces is such that the available commands (see section 6.7.2) and request codes for the ZSSC3230 are the same regardless on the interface type used. Initially after power-up or reset, the I2C slave address is loaded from the on-chip NVM from the Slave_Addr bits [6:0] in register 02HEX; see Table 16). There is a general status byte, which is part of the ZSSC3230’s digital response on READ requests. Every response starts with a status byte followed by the data word. The data word depends on the previous command. It is possible to read the same data more than once if the read request is repeated. The next command invalidates any previous data. Table 9. General Status Byte Bit-Number: 7 6 5 4 3 2 1 0 Meaning: 0 Powered? Busy? Mode Memory Error? ADC Overflow Math Saturation Bit 7 is intentionally not assigned in order to allow for a 1 bit-length time. Bit 6 indicates power: 1 if device is powered, 0 if not powered. Bit 5 indicates whether the ZSSC3230 is busy. The data for the last command is not available yet. No new commands are processed if the device is busy. It is “1” if the device is busy. |
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