TMS320F28075PZPQ datasheet(49/196 Pages) TI

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th(boot-mode)(B)

XRS

(A)

Boot-Mode

Pins

(3.3 V)

DDIO

DDA

(1.2 V)

User-code dependent

Boot-ROM execution starts

Peripheral/GPIO function

Based on boot code

GPIO pins as input

CPU

Execution

Phase

Boot ROM

User-code

I/O Pins

GPIO pins as input (pullups are disabled)

User-code dependent

tw(RSL1)

TMS320F28076, TMS320F28075

www.ti.com

SPRS902I – OCTOBER 2014 – REVISED JUNE 2020

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Product Folder Links: TMS320F28076 TMS320F28075

Specifications

5.9.2.2

Reset Electrical Data and Timing

Table 5-5 shows the reset (XRS) timing requirements. Table 5-6 shows the reset (XRS) switching

characteristics. Figure 5-5 shows the power-on reset. Figure 5-6 shows the warm reset.

Table 5-5. Reset (XRS) Timing Requirements

MIN

MAX

UNIT

th(boot-mode)

Hold time for boot-mode pins

1.5

tw(RSL2)

Pulse duration, XRS low on

warm reset

All cases

3.2

µs

Low-power modes used in

application and SYSCLKDIV > 16

3.2 * (SYSCLKDIV/16)

Table 5-6. Reset (XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

tw(RSL1)

Pulse duration, XRS driven low by device after supplies are

stable

100

µs

tw(WDRS)

Pulse duration, reset pulse generated by watchdog

512tc(OSCCLK)

cycles

The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 4-1.

After reset from any source (see Section 5.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status

of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code

executes after power-on conditions (in debugger environment), the boot code execution time is based on the current

SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

Figure 5-5. Power-on Reset

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