ZSSC3018 Datasheet

© 2020 Renesas Electronics Corporation

6

September 8, 2020

1. IC Characteristics

1.1 Absolute Maximum Ratings

Note: The absolute maximum ratings are stress ratings only. The ZSSC3018 might not function or be operable above the recommended

operating conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to

stresses above the recommended operating conditions might affect device reliability. Renesas does not recommend designing to the “Absolute

Maximum Ratings.”

Table 1.1 Absolute Maximum Ratings

PARAMETER

SYMBOL

Min

TYP

MAX

UNITS

Voltage Reference

Vss

0

–

0

V

Analog Supply Voltage

-0.4

–

3.63

V

Voltage at all Analog and Digital IO Pins

-0.5

–

V

Input Current into any Pin except RES, TEST1, TEST2, TEST3, TEST4,

TEST5, and SS [a], [b]

-100

–

100

mA

Electrostatic Discharge Tolerance – Human Body Model (HBM1) [c]

4000

–

–

V

Storage Temperature

-50

–

130

°C

[a] Latch-up current limit for RES, TEST1, TEST2, TEST3, TEST4, TEST5, and SS: ±70mA.

[b] Latch-up resistance; reference for pin is 0V.

 in series based on MIL 883, Method 3015.7. ESD protection

referring to the Human Body Model is tested with devices in ceramic dual in-line packages (CDIP) during product qualification.

1.2 Operating Conditions

Note: The reference for all voltages is Vss.

Table 1.2 Operating Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Supply Voltage

1.68

–

3.6

V

VDD Rise Time

–

–

200

μs

Bridge Current [a]

–

–

1.8

mA

–

–

16.5

Operation Temperature Range

-40

–

125

°C

External (Parasitic) Capacitance between VDDB and VSS

0.01

–

50

nF

A dynamic power-on-reset circuit is implemented in order to achieve the minimum current consumption in Sleep Mode. The VDD low level, the

subsequent rise time, and the VDD rising slope must meet the requirements in Table 1.3 to guarantee an overall IC reset: lower VDD low levels

allow slower rising of the subsequent on-ramp of VDD. Other combinations might also be possible. For example, the reset trigger can be

influenced by increasing the power-down time and lowering the VDD rising slope requirement. Alternatively, the RES pin can be connected and

used to control safe resetting of the IC. RES is low-active – a VDD-VSS-VDD transition at the RES pin leads to a complete ZSSC3018 reset.