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MPC9456 bảng dữ liệu(PDF) 4 Page - Freescale Semiconductor, Inc

tên linh kiện MPC9456
Giải thích chi tiết về linh kiện  2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
PDF  12 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC9456 bảng dữ liệu(HTML) 4 Page - Freescale Semiconductor, Inc

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MPC9456
MOTOROLA
TIMING SOLUTIONS
4
Table 6: DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input high voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input low voltage
-0.3
0.8
V
LVCMOS
VPP
Peak-to-peak input voltage
PCLK
250
mV
LVPECL
VCMRa
Common Mode Range
PCLK
1.1
VCC-0.6
V
LVPECL
IIN
Input currentb
200
µA
VIN=GND or VIN=VCC
VOH
Output High Voltage
2.4
V
IOH=-24 mAc
VOL
Output Low Voltage
0.55
0.30
V
V
IOL= 24mAb
IOL= 12mA
ZOUT
Output impedance
14 - 17
W
ICCQd
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
a.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b.
Input pull-up / pull-down resistors influence input current.
c.
The MPC9456 is capable of driving 50
Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
d.
ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 7: AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
250b
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
0
0
250b
125
MHz
MHz
FSELx=0
FSELx=1
VPP
Peak-to-peak input voltage
PCLK
500
1000
mV
LVPECL
VCMRc
Common Mode Range
PCLK
1.3
VCC-0.8
V
LVPECL
tP, REF
Reference Input Pulse Width
1.4
ns
tr, tf
PCLK Input Rise/Fall Time
1.0d
ns
0.8 to 2.0V
tPLH
tPHL
Propagation delay
CCLK to any Q
CCLK to any Q
2.2
2.2
2.8
2.8
4.45
4.2
ns
ns
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
ps
ps
tsk(PP)
Device-to-device Skew
2.25
ns
tSK(P)
DCQ
Output pulse skewe
Output Duty Cycle
÷1 output
÷2 output
47
45
50
50
200
53
55
ps
%
%
DCREF = 50%
DCREF = 25%-75%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
a.
AC characteristics apply for parallel output termination of 50
Ω to VTT.
b.
The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
c.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
d.
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e.
Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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