STM32WLE4JC datasheet(38/145 Pages) STMICROELECTRONICS

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Functional overview

STM32WLE5/E4xx

38/145

DS13105 Rev 8

3.14

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.15

Direct memory access controller (DMA)

The DMA (direct memory access) is used to provide high-speed data transfer between

peripherals and memory, as well as memory to memory. Data can be quickly moved by

DMA without any CPU actions. This keeps CPU resources free for other operations.

The DMA controller has 14 channels in total. A full cross matrix allows the peripherals, with

DMA support, to be mapped on any of the available DMA channels. Each DMA channel has

an arbiter for handling the priority between DMA requests.

The DMA main features are listed below:

•

14 independently configurable channels (requests)

•

a full cross matrix between peripherals and all 14 channels and an hardware trigger

possibility through the DMAMUX1

•

software programmable priorities between requests from channels of one DMA (four

levels: very-high, high, medium, low), plus hardware priorities management in case of

equality (example: request 1 has priority over request 2)

•

independent source and destination transfer size (byte, half-word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•

support for circular buffer management

•

three event flags (DMA half-transfer, DMA transfer complete and DMA transfer error),

logically ORed together in a single interrupt request for each channel

•

memory-to-memory transfer

•

peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

•

access to Flash memory, SRAM, APB and AHB peripherals, as source and destination

•

programmable number of data to be transferred (up to 65536)

DMAMUX1 is used to route the peripherals with DMA source support, to any DMA channel.

Table 11. DMA1 and DMA2 implementation

Feature

DMA1

DMA2

Number of channels

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