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STM32WLE4JC bảng dữ liệu(PDF) 130 Page - STMicroelectronics

tên linh kiện STM32WLE4JC
Giải thích chi tiết về linh kiện  Multiprotocol LPWAN 32-bit Arm® Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32WLE4JC bảng dữ liệu(HTML) 130 Page - STMicroelectronics

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Electrical characteristics
STM32WLE5/E4xx
130/145
DS13105 Rev 8
SPI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 25: General operating conditions, with the following configuration:
•
output speed set to OSPEEDRy[1:0] = 11
•
capacitive load C = 30 pF
•
measurements done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 92. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
1.8 < VDD < 3.6 V, Range 1
--
24
MHz
Master transmitter mode
1.8 < VDD < 3.6 V, Range 1
24
Slave receiver mode
1.8 < VDD < 3.6 V, Range 1
24
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V, Range 1
24(2)
Slave mode transmitter/full duplex
1.8 < VDD < 3.6 V, Range 1
24(2)
tsu(NSS) NSS setup time
Slave mode, SPI prescaler = 2
3 x TPCLK
--
-
th(NSS) NSS hold time
Slave mode, SPI prescaler = 2
2 x TPCLK
--
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
TPCLK - 1
TPCLK
TPCLK + 1
tsu(MI)
Data input setup time
Master mode
1
-
-
ns
tsu(SI)
Slave mode
1
-
-
th(MI)
Data input hold time
Master mode
6
-
-
th(SI)
Slave mode
2
-
-
ta(SO)
Data output access time
Slave mode
912
34
tdis(SO) Data output disable time
9
10
16



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