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M24128X-FCU6/TF bảng dữ liệu(PDF) 8 Page - STMicroelectronics |
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M24128X-FCU6/TF bảng dữ liệu(HTML) 8 Page - STMicroelectronics |
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8 / 35 page ![]() 5.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 5.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 5.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 5.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 5.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a start condition. Following this, the bus master sends the device select code, shown in Table 4 on serial data (SDA), most significant bit first. Table 4. Device select code Device type identifier (1) Chip enable address (2) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 C2 C1 C0 RW 1. The most significant bit, b7, is sent first. 2. b3, b2 and b1 are compared with the C2, C1 and C0 values programmed in the chip enable register. When the device select code is received, the device responds only if the b3, b2 and b1 values match the values of the C2, C1 and C0 bits programmed in the chip enable register. If a match occurs, the corresponding device gives an acknowledgment on serial data (SDA) during the 9th bit time. If the device does not acknowledge the device select code, the device de-selects itself from the bus, and goes into standby mode (therefore will not acknowledge the device select code). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. M24128X-FCU Start condition DS12680 - Rev 2 page 8/35 |
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