BLUENRG-LP datasheet(50/72 Pages) STMICROELECTRONICS

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Figure 16. Recommended RSTN pin protection

Note:

The external reset circuit protects the device against parasitic resets.

The user must ensure that the level on the RSTN pin can go below the VIL(RSTN) max. level specified in the

table, otherwise the reset is not taken into account by the device. The external capacitor on RSTN must be

placed as close as possible to the device.

5.3.18

ADC characteristics

Table 37. ADC characteristics (HSI must be set to PLL mode)

Symbol

Parameter

Test conditions

Min. Typ. Max.

Units

Ch_diff_num

Number of channels for

differential mode

QFN48, WLCSP49

Ch_se_num

Number of channels for single

ended mode

QFN48, WLCSP49

IBATADCBIAS

ADC biasing consumption at

battery

Biasing blocks turned on

145

IBATADCACTIVE

ADC active consumption at

battery

ADC activated in differential mode

185

VDDA

Analog supply voltage

1.2

1.32

RAIN

Input impedance

In DC

250

kΩ

Rin

Internal access resistance

VBOOST is enabled for VDD < 2.7 V

550

Ω

Cin

Input sampling capacitor

Sampling period

µs

Tsw

Sampling time

125

Output data rate

200

k samples/s

FRMToutput

Output data format

bits

Latency time

200 kSps

µs

TSTARTUP

Start-up time

From ADC enable to conversion start

µs

DNL

Differential non-linearity

±0.7

LSB

BlueNRG-LP

Operating conditions

DS13282 - Rev 2

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