A6986H datasheet(70/71 Pages) STMICROELECTRONICS

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Figure 51.

Master driving capability to synchronize the A6986H ......................................... 50

Figure 52.

Evaluation board schematic .......................................................... 53

Figure 53.

Magnitude bode plot ............................................................... 56

Figure 54.

Phase margin bode plot ............................................................. 56

Figure 55.

Top layer ....................................................................... 57

Figure 56.

Bottom layer..................................................................... 57

Figure 57.

Efficiency: VIN = 13.5 V - VOUT = 3.3 V - fsw = 500 kHz ....................................... 58

Figure 58.

Efficiency: VIN = 13.5 V - VOUT = 3.3 V - fsw = 500 kHz (log scale)................................ 58

Figure 59.

Efficiency: VIN = 13.5 V - VOUT = 5 V - fsw = 500 kHz ......................................... 59

Figure 60.

Efficiency: VIN = 13.5 V - VOUT = 5 V - fsw = 500 kHz (log scale) ................................. 59

Figure 61.

Efficiency: VIN = 24 V - VOUT = 3.3 V - fsw = 500 kHz ......................................... 60

Figure 62.

Efficiency: VIN = 24 V - VOUT = 3.3 V - fsw = 500 kHz (log scale) ................................. 60

Figure 63.

Efficiency: VIN = 24 V - VOUT = 5 V - fsw = 500 kHz .......................................... 61

Figure 64.

Efficiency: VIN = 24 V - VOUT = 5 V - fsw = 500 kHz (log scale) .................................. 61

Figure 65.

HTSSOP16 package outline.......................................................... 62

A6986H

List of figures

DS12861 - Rev 3

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