R5F52105ADFN datasheet(13/223 Pages) RENESAS

13 / 223 page

R01DS0041EJ0150 Rev.1.50

Page 13 of 221

Oct 18, 2013

RX210 Group

1. Overview

1.3

Block Diagram

Figure 1.2 shows a block diagram.

Figure 1.2

Block Diagram

External bus

BSC

ICUb:

Interrupt controller

DTCa:

Data transfer controller

DMACA:

DMA controller

BSC:

Bus controller

WDTA:

Watchdog timer

IWDTa:

Independent watchdog timer

ELC:

Event link controller

CRC:

CRC (cyclic redundancy check) calculator

SCIc, SCId: Serial communications interface

RSPI:

Serial peripheral interface

RIIC:

2C bus interface

TPUa:

16-bit timer pulse unit

MTU2a: Multi-function timer pulse unit 2

POE2a: Port output enable 2

TMR:

8-bit timer

CMT:

Compare match timer

RTCb:

Realtime clock

DOC:

Data operation circuit

CAC:

Clock frequency accuracy measurement circuit

Clock

generation

circuit

RX CPU

RAM

ROM

Port 7

Port 8

Port 9

Port A

Port B

10-bit D/A converter × 2 channels

Temperature sensor

RIIC × 1 channel

DOC

WDTA

E2 DataFlash

CRC

ELC

RTCb

MTU2a × 6 channels

12-bit A/D converter × 16 channels

CMT × 2 channels (unit 1)

CMT × 2 channels (unit 0)

TMR × 2 channels (unit 1)

TMR × 2 channels (unit 0)

RSPI × 1 channel

DTCa

DMACA × 4

channels

ICUb

CAC

SCId × 1 channel

Port C

Port D

Port E

Port F

Port H

Port J

Port K

Port L

POE2a

IWDTa

Comparator B × 2 channels

Comparator A × 2 channels

Port 3

Port 4

Port 5

Port 6

Port 0

Port 1

Port 2

SCIc × 12 channels

TPUa × 6 channels

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