DS250DF230ZLSR datasheet(49/105 Pages) TI

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DS250DF230

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SNLS590B – AUGUST 2018 – REVISED OCTOBER 2019

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Table 10. Channel Registers, 0 to 39 (continued)

ADDRESS

(HEX)

BITS

DEFAULT

VALUE

(HEX)

MODE

EEPROM

FIELD NAME

DESCRIPTION

RESERVED

EQ_BST3_BIT2_TO_EQ

Read-back of eq_BST3[2] driving the

RESERVED

PRBS_PATTERN_SEL[2]

MSB for the PRBS_PATTERN_SEL

field. Lower bits are found on

Reg_0x30[1:0]. Refer to the Reg_0x30

description on this table.

RESERVED

RATE[2]

Configure PPM register and divider for

a standard data rate.

(Refer to the Programming Guide for

more details)

RATE[1]

RATE[0]

INDEX_OV

If this bit is 1, then Reg_0x39 is to be

used as 4-bit index to the [15:0] array

of EQ settings. The EQ setting at that

index is loaded to the EQ boost

registers going to the analog and is

used as the starting point for adaption.

EN_PPM_CHECK

1: (Default) Enable the PPM to be

used as a qualifier when performing

Lock Detect

0: Remove the PPM check as a lock

qualifier.

RESERVED

DS250DF230:

1: Disable eq_bypass for first 4 indices

0: Enable eq_bypass for first 4 indices

RWSC

CTLE_ADAPT

1: Re-starts CTLE adaptation, self-

clearing

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