CS4210 datasheet(74/102 Pages) NSC

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4.4.16.6

IsochRxIntEvent Register

There are two 32-bit registers to report isochronous receive

context interrupts: IsochRxIntEvent and IsochRxIntMask.

Both registers are set and clear. For all four addresses,

writing a “zero” bit has no effect on the corresponding bit in

the register. The IsochRxIntEvent register contains the

actual interrupt request bits. Each of these bits corre-

sponds to a DMA completion event for the indicated isoch-

ronous receive context. The IsochRxIntMask register is

ANDed with the IsochRxIntEvent register to enable

selected bits to generate processor interrupts. If (IsochRx-

IntMask and IsochRxIntEvent) are not zero, then the Isoch-

RxIntn bit is set to one, and if enabled via the IntMask

to the IsochRxIntEvent Set register can therefore cause an

interrupt (if not otherwise masked). A software write to the

IsochRxIntEvent Clear register clears interrupt conditions

reported in the IsochRxIntEvent register. Reading the Iso-

chRxIntEvent Set register returns the current state of the

IsochRxIntEvent register. Reading the IsochRxIntEvent

Clear register returns the masked version of the IsochRx-

IntEvent register (IsochRxIntEvent and IsochRxIntMask).

The IsochRxIntEvent register reflects the interrupt state of

the isochronous receive contexts. An interrupt is generated

on behalf of an isochronous receive context if a final com-

mand of a DMA descriptor block completes and its i bits are

set to 11b (interrupt always). Upon determining that the

IsochRx interrupt has occurred, software can check the

IsochRxIntEvent register to determine which context(s)

caused the interrupt.

4.4.16.7 IsochRxIntMask Register

The bits in the IsochRxIntMask register have the same for-

mat as the IsochRxIntEvent register. Setting a bit in this

Mask Set register and is cleared by writing a one to the cor-

responding bit in the IsochRxIntMask Clear register. Bits

for all unimplemented contexts read as 0’s. Software can

use this register to determine which contexts are supported

by writing to it with all 1’s then reading it back. Contexts

with a 1 are implemented, and those with a 0 are not.

Table 4-30. BAR0+Offset A0h (Set) and A4h (Clear): IsochRxIntEvent Register

Bit

Name

Access

Reset

Description

31:8

RSVD

Reserved

isochRxInt7

RSC

Undef

Isochronous Receive Contexts Interrupt Event: Set to one when the cor-

responding isochronous receive context interrupts and the Interrupt Mask is

enabled.

isochRxInt6

isochRxInt5

isochRxInt4

isochRxInt3

isochRxInt2

isochRxInt1

isochRxInt0

Table 4-31. BAR0+Offset A8h (Set) and ACh (Clear): IsochRxIntMask Register

Bit

Name

Access

Reset

Description

31:8

RSVD

Reserved

isochRxIntMask7

RSC

Undef

Isochronous Receive Contexts Interrupt Mask Set: Set to one enables

the corresponding bit in the IsochRxIntEvent Register.

isochRxIntMask6

isochRxIntMask5

isochRxIntMask4

isochRxIntMask3

isochRxIntMask2

isochRxIntMask1

isochRxIntMask0

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