AGLP030 datasheet(75/128 Pages) ACTEL

75 / 128 page

IGLOO PLUS Low Power Flash FPGAs

Re vi s i on 11

2 - 61

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-90 • IGLOO PLUS CCC/PLL Specification

For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage

Parameter

Min.

Typ.

Max.

Units

Clock Conditioning Circuitry Input Frequency fIN_CCC

1.5

250

MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC

0.75

250

MHz

Delay Increments in Programmable Delay Blocks 1, 2

360

Number of Programmable Values in Each Programmable Delay Block

Serial Clock (SCLK) for Dynamic PLL3,4

Input Cycle-to-Cycle Jitter (peak magnitude)

100

MHz

Acquisition Time

LockControl = 0

300

µs

LockControl = 1

6.0

Tracking Jitter5

LockControl = 0

2.5

LockControl = 1

1.5

Output Duty Cycle

48.5

51.5

Delay Range in Block: Programmable Delay 1 1, 2

1.25

15.65

Delay Range in Block: Programmable Delay 2 1, 2

0.469

15.65

Delay Range in Block: Fixed Delay 1, 2

3.5

VCO Output Peak-to-Peak Period Jitter FCCC_OUT

Maximum Peak-to-Peak Period Jitter6,7,8

SSO

≤ 2 SSO ≤ 4

SSO

≤ 8

SSO

≤ 16

0.75 MHz to 50 MHz

0.50%

0.60%

0.80%

1.20%

50 MHz to 250 MHz

2.50%

4.00%

6.00%

12.00%

Notes:

1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.

2. TJ = 25°C, VCC = 1.5 V

3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction

temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.

4. The AGLP030 device does not support a PLL.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock

edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter

parameter.

6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying

the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider

settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output

divider settings.

7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.14 V,

VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.

8. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of

each other.Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement

Guidelines" chapter of the ProASIC3 FPGA Fabric User’s Guide.

AGLP030 bảng dữ liệu(PDF) 75 Page - Actel Corporation

AGLP030 bảng dữ liệu(HTML) 75 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL