SL3S4021 datasheet(21/30 Pages) NXP

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NXP Semiconductors

SL3S4011_4021

UCODE I²C

SL3S4011_4021

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Product data sheet

Rev. 3.5 — 18 September 2018

COMPANY PUBLIC

204935

21 / 30

pulses so that the UCODE I2C continues to output the next byte in sequence. To

terminate the stream of bytes, the bus master must not acknowledge the last byte, and

must generate a Stop condition, as shown in Figure 8.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output.

11.8.4 Acknowledge in Read mode

For all Read commands, the UCODE I2C waits, after each byte read, for an

acknowledgment during the 9th bit time. If the bus master does not drive Serial Data

(SDA) low during this time, the UCODE I2C terminates the data transfer and switches to

its Standby mode.

11.8.5 EPC memory bank handling

After the last memory address within one EPC memory bank, the address counter 'rolls-

over' to the next EPC memory bank, and the UCODE I2C continues to output data from

memory address 00h in the successive EPC memory bank.

Example: EPC Bank 01 → EPC Bank 10 → EPC Bank 11 → EPC Bank 01

12 RF interface/I2C interface arbitration

The UCODE I2C needs to arbitrate the EEPROM access between the RF and the I2C

interface.

The arbitration is implemented as following:

• First come, first serve strategy - the interface which provides data by having a first valid

preamble on RF envelope (begin of a command) or a start condition and a valid I2C

device address on the I2C interface will be favored.

• I2C access to the chip memory is possible regardless if it is in the EPC Gen2 secured

state or not

• During an I2C command, starting with an I2C start followed by valid I2C device address

and ending with an I2C stop condition, any RF command is ignored.

• During any EPC Gen2 command, any I2C command is ignored

There are known limitations for applications where both interfaces are powered. For

details refer to Ref. 6.

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