SL3S4021 datasheet(16/30 Pages) NXP

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NXP Semiconductors

SL3S4011_4021

UCODE I²C

SL3S4011_4021

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 18 September 2018

COMPANY PUBLIC

204935

16 / 30

10.4.3 Via I2C

The EPC Gen2 locking bits for the memory banks are also accessible via the I2C

interface for read and write operation and are located at the I2C address 803Ch. But it is

not possible to read and write the access and kill password.

Data Byte 1

Mask field

Action field

Kill PWD

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

Skip/

write

X X X X X X

Access PWD

User memory

EPC memory

TID memory

Kill PWD

n/a

permalock

n/a

PWD

write

PWD

write

PWD

write

Access PWD

User memory

EPC memory

TID memory

Data Byte 2

LSB

MSB

Data Byte 3

Data Byte 4

LSB

MSB

aaa-003734

Figure 5. I2C memory bank lock write and read access

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