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MAS3504D bảng dữ liệu(PDF) 18 Page - Micronas

tên linh kiện MAS3504D
Giải thích chi tiết về linh kiện  G.729 Annex A Voice Codec
PDF  40 Pages
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nhà sản xuất  MICRONAS [Micronas]
Trang chủ  http://www.micronas.com
Logo MICRONAS - Micronas

MAS3504D bảng dữ liệu(HTML) 18 Page - Micronas

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MAS 3504D
18
Micronas
3.5.2.4. Pause and Mute
If the pause bit is set, the processing continues until
the current page is finished and then en-/decoding is
paused. The pause mode lasts until the pause bit is
cleared again or the mode is set to 0.
If the mute bit is set, the output is muted immediately.
Note that the other bits of the UserControl register
have to stay on their old values when switching to
pause mode.
3.5.3. Volume Control (Reg. FChex)
Volume control is implemented in the MAS 3504D. It
allows to adjust the output volume linear from 0hex
(silence) to 7FFFFhex (original volume).
3.5.4. Interface Control
All the interface control registers have to be written
before the encoder or decoder is started by writing to
the UserControl register. Otherwise they have no
effect until the operation mode is changed.
3.5.4.1. Wordlength Control (Reg. 74hex)
A value of 0hex sets wordlength on SDI and SDO inter-
faces to 32 bit. 1hex sets wordlength to 16 bit.
3.5.4.2. Input Configuration (Reg. 61hex)
The content of this register is set on startup by the
firmware. Additional to the Wordlength setting for the
serial interfaces, some other settings can be made.
3.5.4.3. Output Configuration (Reg. E1hex)
The content of this register is set on startup by the
firmware. Additional to the Wordlength setting for the
serial interfaces, some other settings can be made.
3.5.5. Hardware Control (Reg. FAhex)
The HWControl register is used to set special opera-
tion options.
If the page headers bit is 0, a header frame is trans-
ferred in front of each page of 50 data frames. If the
header bit is 1, all the frames are G.729 data frames.
Bits 2 and 1 are used to select input channels for
encoding. If both bits are set to 0, the left and right
channel are added to get the mono input signal. If only
one of this bits is 1, only the corresponding channel is
used as input.
Fig. 3–2: Schematic timing of the data transmission with preceeding header
...
...
...
10ms 10ms ...
...
header
page frame
1
frame
2
frame
3
frame
49
frame
49
header
page frame
51
frame
52
frame
99
frame
100 header
page frame
101
frame
102
$64 $6d $72 $31 $64 $61 $74 $61 $f4 $01
byte
2
byte
1
byte
4
byte
3
byte
6
byte
5
byte
8
byte
7
byte
10
byte
9



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