ADSP-21486KSWZ-2AB datasheet(50/71 Pages) AD

50 / 71 page

Rev. H

Page 50 of 71

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPI Interface—Slave

Table 50. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

tSPICLKS

Serial Clock Cycle

4 × tPCLK – 2

tSPICHS

Serial Clock High Period

2 × tPCLK – 2

tSPICLS

Serial Clock Low Period

2 × tPCLK – 2

tSDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × tPCLK

tHDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

2 × tPCLK

tSSPIDS

Data Input Valid to SPICLK edge (Data Input Set-up Time)

tHSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

tSDPPW

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × tPCLK

Switching Characteristics

tDSOE

SPIDS Assertion to Data Out Active

7.5

tDSOE

SPIDS Assertion to Data Out Active (SPI2)

7.5

tDSDHI

SPIDS Deassertion to Data High Impedance

10.5

tDSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

10.5

tDDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

9.5

tHDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

2 × tPCLK

tDSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0)

5 × tPCLK

1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the “Serial Peripheral Interface Port” chapter of

the hardware reference manual.

Figure 35. SPI Slave Timing

tSPICHS

tSPICLS

tSPICLKS

tHDS

tSDPPW

tSDSCO

tDSOE

tDDSPIDS

tDSDHI

tHDSPIDS

tHSPIDS

tSSPIDS

tDSDHI

tDSOV

tHSPIDS

tHDSPIDS

SPIDS

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPICLK

(CP = 0,

CP = 1)

(INPUT)

tSSPIDS

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