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ADP1032ACPZ-3-R7 bảng dữ liệu(PDF) 36 Page - Analog Devices |
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ADP1032ACPZ-3-R7 bảng dữ liệu(HTML) 36 Page - Analog Devices |
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36 / 37 page ![]() ADP1032 Data Sheet Rev. 0 | Page 36 of 37 PCB LAYOUT CONSIDERATIONS To achieve optimum efficiency, proper regulation, strong stability, and low noise, a well-designed PCB layout is required. Follow these guidelines when designing PCBs: Keep the input bypass capacitor (CIN) close to the VINP pin and the PGNDP pin. Keep the high current switching paths as short as possible. These paths include the connections between the following: CIN, the VINP pin, the primary winding of the transformer, and the PGNDP pin The VOUT1 pin, CFLYBK, Diode 1 (D1), the secondary winding of the transformer, and the SGND2 pin The VOUT2 pin, the SW2 pin, Inductance 1 (L1), CBUCK, and the SGND2 pin Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and EMI. Avoid routing high impedance traces near any node connected to the SWP pin and SW2 pin or near the L1 inductor or the T1 transformer to prevent radiated switching noise injection. Place the feedback resistors as close to the FB1 pin as possible to prevent high frequency switching noise injection. To minimize EMI, perform the following actions: Place the MVDD decoupling capacitor (C1) as close to the MVDD pin (Pin 39) and the MGND pin (Pin 3) as possible. Place the SVDD1 decoupling capacitor (C3) as close to the SVDD1 pin (Pin 10) and the SGND1 pin (Pin 5) as possible. Place the SVDD2 decoupling capacitor (C7) as close to the SVDD2 pin (Pin 20) and the SGND2 pin (Pin 16) as possible. Figure 78 shows a suggested top layer layout for the ADP1032 to minimize EMI. D1 U1 CIN CFLYBK CBUCK C3 L1 C7 R10 R9 T1 MVDD D2 R7 C6 OR D3 VINP PGNDP MGND SGND VOUT2 VOUT1 SGND 22mm C1 Figure 78. Suggested Top Layer Layout |
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