MPF5023AMBA0ES datasheet(29/91 Pages) NXP

29 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

29 / 91

Table 24. Fault timer register configuration

OTP bits

OTP_TIMER_FAULT [3:0]

Functional bits

TIMER_FAULT [3:0]

Timer value

(ms)

0000

0001

0010

0011

0100

0101

0110

0111

128

1000

256

1001

512

1010

1024

1011

2056

1100

Reserved

1101

Reserved

1110

Reserved

1111

Disabled

Each voltage regulator has a dedicated I2C bit that is used to bypass the fault detection

mechanism for each specific fault.

SWx_ILIM_BYPASS

• 0 = ILIM protection enabled

• 1 = ILIM fault bypassed

SWx_OV_BYPASS

• 0 = OV protection enabled

• 1 = OV fault bypassed

SWx_UV_BYPASS

• 0 = UV protection enabled

• 1 = UV fault bypassed

Table 25. Fault bypass bits

Regulator

Bit to bypass a current

limit

Bit to bypass an

undervoltage

Bit to bypass an

overvoltage

SWx

SWx_ILIM_BYPASS

SWx_UV_BYPASS

SWx_OV_BYPASS

The default value of the OV_BYPASS, UV_BYPASS and ILIM_BYPASS bits upon power

up can be configured by their corresponding OTP bits.

Bypassing the fault detection prevents the specific fault from starting any of the protective

mechanism:

• Increment the counter

• Start the fault timer

• Disable the regulator if the corresponding _STATE bit is 0

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