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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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IIS2DLPC bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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IIS2DLPC bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 69 page  DocID031788 Rev 4 17/69 IIS2DLPC Mechanical and electrical specifications 69 Table 9. I2C high-speed mode specifications at 1 MHz and 3.4 MHz Symbol Parameter Min Max Unit Fast mode plus(1) fSCL SCL clock frequency 0 1 MHz tHD;STA Hold time (repeated) START condition 260 - ns tLOW Low period of the SCL clock 500 - tHIGH High period of the SCL clock 260 - tSU;STA Setup time for a repeated START condition 260 - tHD;DAT Data hold time 0 - tSU;DAT Data setup time 50 - trDA Rise time of SDA signal - 120 tfDA Fall time of SDA signal - 120 trCL Rise time of SCL signal 20*Vdd/5.5 120 tfCL Fall time of SCL signal 20*Vdd/5.5 120 tSU;STO Setup time for STOP condition 260 - Cb Capacitive load for each bus line - 550 pF tVD;DAT Data valid time - 450 ns tVD;ACK Data valid acknowledge time - 450 VnL Noise margin at low level 0.1Vdd - V VnH Noise margin at high level 0.2Vdd - tSP Pulse width of spikes that must be suppressed by the input filter 050 ns High-speed mode(1) fSCLH SCLH clock frequency 0 3.4 MHz tSU;STA Setup time for a repeated START condition 160 - ns tHD;STA Hold time (repeated) START condition 160 - tLOW Low period of the SCLH clock 160 - tHIGH High period of the SCLH clock 60 - tSU;DAT Data setup time 10 - tHD;DAT Data hold time 0 70 trCL Rise time of SCLH signal 10 40 trCL1 Rise time of SCLH signal after a repeated START condition and after an acknowledge bit 10 80 tfCL Fall time of SCLH signal 10 40 trDA Rise time of SDAH signal 10 80 tfDA Fall time of SDAH signal 10 80 tSU;STO Setup time for STOP condition 160 - Cb Capacitive load for each bus line - 100 pF VnH Noise margin at high level 0.2Vdd - V tSP Pulse width of spikes that must be suppressed by the input filter 010 ns 1. Data based on characterization, not tested in production |
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