MGC3140 datasheet(31/49 Pages) MICROCHIP

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I2C Master Read Bit Timing

Master read is to receive position data, gesture reports and command responses from the MGC3140.

The timing diagram is shown below:

Figure 7-2. I2C Master Read Bit Timing Diagram

Address

R/W

ACK

Data

Address Bits Latched in

Data Bits Valid Out

SCL may be stretched

Start Bit

Stop Bit

SDA

SCL

•

Address bits are latched into the MGC3140 on the rising edges of SCL.

•

Data bits are latched out of the MGC3140 on the rising edges of SCL.

•

ACK bit:

–

MGC3140 presents the ACK bit on the ninth clock for address acknowledgment

–

I2C master presents the ACK bit on the ninth clock for data acknowledgment

•

The I2C master must monitor the SCL pin prior to asserting another clock pulse, as the MGC3140

may be holding off the I2C master by stretching the clock.

I2C Communication Steps

SCL and SDA lines are Idle high.

I2C master presents Start bit to the MGC3140 by taking SDA high-to-low, followed by taking SCL

high-to-low.

I2C master presents 7-bit address, followed by a R/W = 1 (Read mode) bit to the MGC3140 on

SDA, at the rising edge of eight master clock (SCL) cycles.

MGC3140 compares the received address to its Device ID. If they match, the MGC3140

acknowledges (ACK) the master sent address by presenting a low on SDA, followed by a low-high-

low on SCL.

I2C master monitors SCL, as the MGC3140 may be clock-stretching, holding SCL low to indicate

that the I2C master should wait.

I2C master receives eight data bits (MSB first) presented on SDA by the MGC3140, at eight

sequential I2C master clock (SCL) cycles. The data is latched out on SCL falling edges to ensure it

is valid during the subsequent SCL high time.

If data transfer is not complete, then:

–

I2C master acknowledges (ACK) reception of the eight data bits by presenting a low on SDA,

followed by a low-high-low on SCL.

–

Go to Step 5.

If data transfer is complete, then:

–

I2C master acknowledges (ACK) reception of the eight data bits and a completed data

transfer by presenting a high on SDA, followed by a low-high-low on SCL.

I2C Master Write Bit Timing

I2C master write is to send supported commands to the MGC3140. The timing diagram is shown below:

MGC3140

Interface Description

DS40002037A-page 31

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