MCP1799 datasheet(11/25 Pages) MICROCHIP

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DS20006248A-page 11

MCP1799

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

3.1

Ground Pin (GND)

For optimal noise and Power Supply Rejection Ratio

(PSRR) performance, the GND pin of the LDO should

be tied to an electrically “quiet” circuit ground. This will

ensure the LDO power supply rejection ratio and noise

device performance. The GND pin of the LDO conducts

only ground current, so a wide trace is not required. For

applications that have switching or noisy inputs, tie the

GND pin to the return of the output capacitor. Ground

planes help lower the inductance and as a result,

reduce the effect of fast current transients.

3.2

Regulated Output Voltage Pin

(VOUT)

The VOUT pin is the regulated output voltage VR of the

LDO. A minimum output capacitance of 1 µF is

required for the LDO to ensure the stability in all the typ-

ical applications. The MCP1799 is stable with ceramic

capacitors. See Section 4.2, Output Capacitance

Requirements for output capacitor selection guidance.

3.3

Input Voltage Supply Pin (VIN)

Connects the voltage source to VIN. If the input voltage

source is located several inches away from the LDO, or

the input source is a battery, it is recommended that an

input capacitor be used. A typical input capacitance

value of 1 µF to 10 µF should be sufficient for most

applications. The type of capacitor used is ceramic.

However, the low ESR characteristics of the ceramic

capacitor will yield better noise and PSRR performance

at high frequency.

TABLE 3-1:

PIN FUNCTION TABLE

SOT 23-3

SOT 223-3

Symbol

Description

GND

Ground

VOUT

Regulated Output Voltage VR

VIN

Input Voltage Supply

—4

TAB

Exposed Thermal Pad, connected internally to GND

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