ELD5016 datasheet(16/38 Pages) EMC

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eLD5016

8-Bit Microcontroller



Product Specification (V1.0) 2.16.2017

(This specification is subject to change without prior notice)

Sub-clock

32.768kHz

switch

System

clock

LPF

1/N

1/M

447.8293kHz ~17.9132MHz

ENPLL

CLK2 ~ CLK0

PLL

Figure 5-5

Correlation between 32768 Hz and Main clock

Bits 5 ~ 3 (CLK2 ~ 0): Main clock select bits.

User can choose different frequencies for the main clock through CLK1

and CLK2. All clock selections are listed below.

PLLEN

CLK2

CLK1

CLK0

Sub clock

Main clock

CPU clock

32768 Hz

447.829 kHz

447.829 kHz (Normal mode)

32768 Hz

895.658 kHz

895.658 kHz (Normal mode)

32768 Hz

1.791 MHz

1.791 MHz (Normal mode)

32768 Hz

3.582 MHz

3.582 MHz (Normal mode)

32768 Hz

7.165 MHz

7.165 MHz (Normal mode)

32768 Hz

10.747 MHz

10.747 MHz (Normal mode)

32768 Hz

14.331 MHz

14.331 MHz (Normal mode)

32768 Hz

17.913 MHz

17.913 MHz (Normal mode)

on’t care

32768 Hz

on’t care

32768 Hz (Green mode)

Bit 2: Undefined bit, set to

“0” at all time

Bit 1 (STA_VR):

Status flag for voice ROM operation

0: Voice ROM busy

1: Voice ROM data ready

When this flag is “0”, the bus of the voice ROM is busy processing its

data. When this flag is “1”, the bus of the Voice ROM is on standby and

its data is ready for users to read.

Bit 0 (RPAGE): Change R PAGE 5 to another page

0: R5 PAGE0

1: R5 PAGE1

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