ELD5016 datasheet(15/38 Pages) EMC

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eLD5016

8-Bit Microcontroller

Product Specification (V1.0) 2.16.2017

 11

(This specification is subject to change without prior notice)

5.1.11

RA (MCUC: CPU Power Saving, PLL, Main Clock Selection,

R Page)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IDLE

ENPLL

CLK2

CLK1

CLK0

STA_VR

RPAGE

R/W-0

RW-0

R-0

R-1

RW-0

Bit 7 (IDLE): Idle mode/Sleep mode select bit

0: Sleep mode

1: Idle mode

This bit will determine which mode to go after SLEP instruction.

These two modes can be awakened by TCC clock, Watchdog timer

(WDT), Ports 97~96, or Ports 70~73,

and run from “SLEP” next

instruction.

Wakeup

Signal

Sleep mode

Idle mode

Green mode

Normal mode

RA(7,6) = (0,0)

+ SLEP

RA(7,6) = (1,0)

+ SLEP

RA(7,6) = (x,0)

no SLEP

RA(7,6) = (x,1)

no SLEP

TCC time out

Wake-up

+ Interrupt

+ Next instruction

Interrupt

WDT time out

Reset

Wake-up

+ Next instruction

Reset

Ports 96, 97

Reset

Wake-up

+ Next instruction

Ports 70 ~ 73

Reset

Wake-up

+ Interrupt

+ Next instruction

Interrupt

P73 ~ P70's wakeup functions are controlled by IOCF (1, 2, 3) and ENI

instructions.

CONT REGISTER Bit 7 defines whether P70's wakeup signal is a rising

or falling edge.

Port 97, Port 96, Port 73, Port 72 and Port 71's wake-up patterns are

falling edge trigger signals.

Bit 6 (ENPLL): PLL's power control bit is CPU mode control register

0: Disable PLL

1: Enable PLL

If PLL is enabled, CPU will operate at normal mode (high frequency).

Otherwise, it will run at green mode (low frequency, 32768 Hz).

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