ATXMEGA8E5 datasheet(54/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 54

ATxmega32E5/16E5/8E5

26. XCL – XMEGA Custom Logic Module

26.1 Features



Two independent 8-bit timer/counter with:



Period and compare channel for each timer/counter



Input Capture for each timer



Serial peripheral data length control for each timer



Timeout support for each timer



Timer underflow interrupt/event



Compare match or input capture interrupt/event for each timer



One 16-bit timer/counter by cascading two 8-bit timer/counters with:



Period and compare channel



Input capture



Timeout support



Timer underflow interrupt/event



Compare match or input capture interrupt/event



Programmable lookup table supporting multiple configurations:



Two 2-input units



One 3-input unit



RS configuration

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Duplicate input with selectable delay on one input or output



Connection to external I/O pins, event system or one selectable USART



Combinatorial Logic Functions using programmable truth table:



AND, NAND, OR, NOR, XOR, XNOR, NOT, MUX



Sequential Logic Functions:



D-Flip-Flop, D Latch, RS Latch



Input sources:



From external pins or the event system



One input source includes selectable delay or synchronizing option



Can be shared with selectable USART pin locations



Outputs:



Available on external pins or event system

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Includes selectable delay or synchronizing option

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Can override selectable USART pin locations



Operates in active mode and all sleep modes

26.2 Overview

The XMEGA Custom Logic module (XCL) consists of two sub-units, each including 8-bit timer/counter with flexible settings,

peripheral counter working with one software selectable USART module, delay elements, glue logic with programmable

truth table and a global logic interconnect array.

The timer/counter configuration allows for two 8-bits timer/counters. Each timer/counter supports normal, compare and

input capture operation, with common flexible clock selections and event channels for each timer. By cascading the two 8-

bit timer/counters, the XCL can be used as a 16-bit timer/counter.

The peripheral counter (PEC) configuration, the XCL is connected to one software selectable USART. This USART con-

trols the counter operation, and the PEC can optionally control the data length within the USART frame.

The glue logic configuration, the XCL implements two programmable lookup tables (LUTs). Each defines the truth table

corresponding to the logical condition between two inputs. Any combinatorial function logic is possible. The LUT inputs can

be connected to I/O pins or event system channels. If the LUT is connected to the USART0 pin locations, the data lines

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