UPD360 datasheet(160/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 160

 2016-2017 Microchip Technology Inc.

11.4.3.9

RX Error Interrupt Enable Register (RX_ERR_IRQ_EN)

Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-

ation is affected. The RX Error Interrupt Status Register (RX_ERR_IRQ_STAT) will still reflect the status of the event.

All interrupts are disabled after POR.

11.4.3.10

Power Management Interrupt Enable and Control Register (PM_IRQ_EN)

Setting a bit in this register will enable to corresponding source to generate an interrupt. Note that only interrupt gener-

ation is affected. The Power Management Interrupt Status Register (PM_IRQ_STAT) will still reflect the status of the

event.

All interrupts are disabled after POR. This register also enables clock start and stop requests.

Address:

1A88h

Size:

8 bits

Bits

Description

Type

Default

DBG_EVENT_EN

Setting this bit enables the DBG_EVENT interrupt.

R/W

6:4

RESERVED

RX_BAD_PKT_EN

Setting this bit enables the RX_BAD_PKT interrupt.

R/W

RX_BUF_OVR_RUN_EN

Setting this bit enables the RX_BUF_OVR_RUN interrupt.

R/W

RX_PCOL_ERROR_EN

Setting this bit enables the RX_PCOL_ERROR interrupt.

R/W

RX_PKT_DROPPED_EN

Setting this bit enables the RX_PKT_DROPPED interrupt.

R/W

Address:

1A89h

Size:

8 bits

Bits

Description

Type

Default

7:4

RESERVED

UPD_CLK_STOP_EN

If this bit is set, the MAC, upon going idle, will request that the system clock be

stopped.

If this bit is cleared, software is responsible to return the device to sleep mode.

This bit does not affect the wake up interrupt (UPD_ACT_WS) generation.

Note:

This bit does not affect the MAC's indication that it requires the

clock. Even if this bit is cleared, the MAC, once it is idle, will indi-

cate that it does not need the clock.

R/W

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