UPD360 datasheet(24/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 24

 2016-2017 Microchip Technology Inc.

This is not relevant for subsequent writes after a new Start condition, since a new register address (with its DIR subfield)

must then be included. However, this would affect the address used by any subsequent read without first resetting the

For both single and multiple writes, if the master sends an unexpected start or stop condition, the device will stop imme-

diately and will respond to the next sequence as needed.

The data write to a multi-byte register may be delayed until after all bits are input. In the event that the full register is not

written (master sends a start or a stop condition occurs unexpectedly), the write may be considered invalid and the reg-

ister not affected. Multiple registers may be written in a multiple write cycle, each one being written in sequence. I2C

writes must not be performed to unused register addresses.

Figure 5-5 illustrates a typical single and multiple register write.

5.2.8

SPECIAL CSR HANDLING

5.2.8.1

Live Bits

Register values are latched (registered) at the beginning of each register read to prevent the host from reading a chang-

ing value. The latching occurs individually per register in a multiple register read sequence.

5.2.8.2

Change-on-Read Registers and FIFOs

Any single-byte register that triggers a side-effect from a read operation (for example, containing “clear on read” bits, or

advancing a FIFO structure) triggers only after the host has begun accessing the value. The value seen by the master

will always be the original value and never the updated result of the side-effect.

For a multiple-byte register that is considered a single unit, the change may be delayed until all bytes of the register

have been read. In the event that the host sends a no-acknowledge on one of the first bytes of a multi-byte register, or

a start or stop condition occurs unexpectedly before the acknowledge of the full register, the read may be considered

invalid and the side-effect not triggered.

Registers read in multiple-register read access will trigger multiple side-effects, occurring as they are read. The following

registers have read side-effects:

• Watchdog Count Register (WDT_COUNT)

FIGURE 5-5:

I2C SLAVE WRITES

Multiple Register Writes

Single Register Write

R/~W

Control Byte

Address Byte 1

Address Byte 0

13 12 11 10

Data Byte

Data Byte 1

. D

Data Bytes

2 — (n-1)

Data Byte n

. D

R/~W

Control Byte

Address Byte 1

Address Byte 0

13 12 11 10

DIR

Inc /

Dec /

Static

DIR

Inc /

Dec /

Static

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