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UPD360 bảng dữ liệu(PDF) 30 Page - Microchip Technology

tên linh kiện UPD360
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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UPD360 bảng dữ liệu(HTML) 30 Page - Microchip Technology

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UPD360
DS00002084C-page 30
 2016-2017 Microchip Technology Inc.
Figure 6-3 illustrates a typical SPI single and multiple register write.
6.2.5
SPECIAL CSR HANDLING
6.2.5.1
Live Bits
Register values are latched (registered) at the beginning of each register read to prevent the host from reading a chang-
ing value. The latching occurs individually per register in a multiple register read sequence.
6.2.5.2
Change-on-Read Registers and FIFOs
Any single-byte register that triggers a side-effect from a read operation (for example, containing “clear on read” bits, or
advancing a FIFO structure) triggers only after the host has begun accessing the value. The value seen by the master
will always be the original value and never the updated result of the side-effect.
For a multiple-byte register that is considered a single unit, the change may be delayed until all bytes of the register
have been read. In the event that the host sends a no-acknowledge on one of the first bytes of a multi-byte register, or
a start or stop condition occurs unexpectedly before the acknowledge of the full register, the read may be considered
invalid and the side-effect not triggered.
Registers read in multiple-register read access will trigger multiple side-effects, occurring as they are read. The following
registers have read side-effects:
• Watchdog Count Register (WDT_COUNT)
6.2.5.3
Live Bits that are also Change-on-Read
As described above, the current value from a register with live bits (as is the case of any register) is captured and latched
as output data, and Change on Read bits are then changed in the original register. To prevent loss of a hardware event
that occurs following the data capture but before the Change on Read, these hardware events are held pending until
after the read action and after any change due to the read. This sequence also ensures an edge in the bit due to the
hardware event.
FIGURE 6-3:
SPI WRITE
SPI Write Single Register
SPI_CLK (Mode 0)
SPI_DI
00
0
0
X
Instruction
1
Address
SPI_DO
Data
A
1
3
SPI Write Multiple Registers
00
D
7
D
6
D
5
Z
X
SPI_CLK (Mode 3)
SPI_CS
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
2
9
3
0
3
1
3
2
X
X
2
9
3
0
3
1
3
2
D
2
D
0
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SPI_CLK (Mode 0)
SPI_DI
00
0
0
X
Instruction
Address
SPI_DO
A
1
3
...
00
Z
SPI_CLK (Mode 3)
SPI_CS
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
X
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
D
7
D
6
D
5
D
2
D
0
...
D
7
D
6
D
5
X
...
D
1
D
1
Data 1...
Data m
Data m+1... Data n
...
0
1
0
Inc / Dec /
Static
DIR
(Irrelevant to 1-byte Writes)
Inc / Dec /
Static
DIR
2
8
2
8
D
4
D
3
D
2
D
0
D
1



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