UPD360 datasheet(152/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 152

 2016-2017 Microchip Technology Inc.

11.4.2.21

RX FIFO Write Head Pointer Plus One Register (RX_FIFO_WR_HEAD_PTR_PLUS_ONE)

This register contains the RX FIFO write head pointer plus one. This pointer indicates where the next received packet

starts plus one. This register is for debug and test purpose only and should not normally be written.

Software must maintain coherency between this and the other Write Pointer Registers.

There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.

It is assumed that this register is only written while there is no active receive.

11.4.2.22

RX FIFO Write Head Pointer Plus One Control Bits Register

(RX_FIFO_WR_HEAD_PTR_PLUS_ONE_CTL_BITS)

This register contains the auxiliary control bits of the RX FIFO write head pointer plus one. This register is for debug and

test purpose only and should not normally be written.

Software must maintain coherency between this and the other Write Pointer Registers.

There is no hardware holding register to maintain write coherency between this and the other Write Pointer Registers.

It is assumed that this register is only written while there is no active receive.

Address:

1A56h

Size:

8 bits

Bits

Description

Type

Default

RESERVED

6:0

RX_FIFO_WR_HEAD_PTR_PLUS_ONE

This field contains the RX FIFO write head pointer plus one.

R/W

0000001b

Address:

1A57h

Size:

8 bits

Bits

Description

Type

Default

7:1

RESERVED

RX_FIFO_WR_HEAD_PTR_PLUS_ONE_WRAP

This field toggles each time the RX FIFO write head pointer plus one wraps

past the top of the RAM (location 127).

R/W

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