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UPD360 bảng dữ liệu(PDF) 147 Page - Microchip Technology |
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UPD360 bảng dữ liệu(HTML) 147 Page - Microchip Technology |
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147 / 221 page  2016-2017 Microchip Technology Inc. DS00002084C-page 147 UPD360 11.4.2.9 RX Duplicate Packet Count Register (RX_DUP_PKT_CNT) This register keeps track of the number of the number of duplicate packets received. It is applicable only when Automatic Response Mode is enabled. This register is for debug purpose only. If enabled, an interrupt can be generated when the count of this register reaches 128. 11.4.2.10 RX Hard Reset Detection Window Register (RX_HR_DET_WINDOW) 11.4.2.11 RX Last GoodCRC Packet High Byte Register (RX_LAST_GCRC_PKT_HI) Address: 1A48h Size: 8 bits Bits Description Type Default 7:0 DUP_PKT_CNT Number of duplicate packets received. Applicable when Auto Response Mode is enabled. When the value of this register becomes greater than 127, the DBG_EVENT bit in the RX Interrupt Status Register (RX_IRQ_STAT) will be set. Any write to this register will clear all bits. R/WAC 00h Address: 1A49h Size: 8 bits Bits Description Type Default 7 RESERVED RO - 6:0 RX_HR_DET_WINDOW Value of Hard Reset detection window in number of bits. This field determines when a detected Hard Reset or Cable Reset will be con- sidered valid. R/W 1011110b Address: 1A4Ah Size: 8 bits Bits Description Type Default 7:0 RX_LAST_GCRC_PKT_HI Bits [15:8] of received GoodCRC message. This register is only valid when auto-retry is enabled. Since GoodCRC mes- sage in auto-retry mode is not stored in the RX queue, this register provides a means for software to examine the last GoodCRC message received. RO 00h |
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