UPD360 datasheet(118/221 Pages) MICROCHIP

118 / 221 page

UPD360

DS00002084C-page 118

 2016-2017 Microchip Technology Inc.

The timeout value for CRCReceiveTimer is programmable via the TRECEIVE field in the RX tReceive Time Register

(RX_TRECEIVE_TIME) in multiples of 10 uSec.

This timer can be used by software as the BISTReceiveErrorTimer in the BIST TX mode (the device does not automat-

ically time BISTReceiveError) and as the CRCReceiveTimer when not using automatic retry or wait for GoodCRC

modes.

11.1.8

ABORTING A TX IN PROCESS

Software can abort a transmission that has already started by issuing an abort via the ABORT bit in the TX Control Reg-

ister B (TX_CTL_B). The packet will be aborted as follows based on current phase of transmission:

• If packet transmission had not yet started because the device was waiting for the turn-around timer to expire or

line to become idle, transmission will be aborted immediately.

• If the current phase is Preamble, the device will complete transfer of the current bit, append EOP, and turn the

transmitter off.

• If the current phase is SOP, Data, or CRC, the device will complete transfer of the current nibble, append EOP,

and turn the transmitter off.

A Hard Reset should follow this operation, which is the software's responsibility.

11.2

PD MAC Receiver

The PD MAC receiver is comprised of three major blocks:

• RX Queue

• RX Control

• RX Comm

The RX Queue is where software reads the received messages.

The RX Control implements the necessary control logic. It is responsible for validating the received packet, updating the

RX Queue status, and triggering automatic responses, if required.

The RX Comm is comprised of the Clock and Data Recovery (CDR), RX DES (de-serializer) (serial-to-parallel converter,

4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to detect valid packet

reception.

The following sub-sections describe the various blocks and sub-blocks in more detail.

11.2.1

RX QUEUE

The decoded RX data (header, data objects, and CRC) is saved into an integrated 128 byte RX FIFO. The RX FIFO that

is capable of storing multiple packets and provides read and write pointers.

Two bytes are added to the beginning of each packet. Byte 0 holds the packet status (SOP type and the legacy “buffer”

valid bit) and byte 1 holds the packet length. An option exists to swap these values (length in byte 0, status in byte 1)

and add one to the packet length (to account for the status byte). This option is used for an SMBus like block read where

the first byte read indicates the length of the transfer and the remaining bytes (the status and the packet) follow. Note

that the packet includes the 4 byte CRC, which is included in the length.

The following sub-sections present details of how the write and read interfaces to the FIFO appear.

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