TLE8110ED datasheet(40/74 Pages) INFINEON

40 / 74 page

Data Sheet

Rev. 1.0

2018-03-07

TLE8110ED

Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

16 bit SPI Interface

11.3

Electrical Characteristics 16 bit SPI Interface

Table 13

Electrical Characteristics: 16 bit SPI Interface

3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Input Characteristics (CS, SCLK, SI)

L level of pin

S_CS,

S_CLK,

S_SI,

VS_CSI

VS_CLKl

VS_SIl

-0.3

–

VCC* 0.2 V

–

P_11.3.1

H level of pin

S_CS,

S_CLK,

S_SI,

VS_CSh

VS_CLKh

VS_SIh

VCC* 0.4 –

VCC

V–

P_11.3.2

Hysteresis Input Pins

VS_CShy

VS_CLKhy

VS_SIhy

100 300

mV –

P_11.3.3

Input Pin pull-down Current

S_CLK, S_SI

IS_CLKh

IS_Slh

µA

VIN = 5V

P_11.3.4

IS_CLKl

IS_Slh

2.4

–

µA

VIN = 0.6V 1)

Input Pin pull-up Current

S_CS

IS_CSh

-4

–

µA

VS_CS = 2V,

VCC = 5V

P_11.3.5

IS_CSl

-20

-40

-85

µA

VS_CS = 0 V,

VCC = 5V

Output Characteristics (SO)

L level output voltage

VS_SOl

0–

0.4

IS_SO = -2 mA

P_11.3.6

H level output voltage

VS_SOh

Vcc -

0.4 V

–

Vcc

–

IS_SO= 1.5 mA

P_11.3.7

Output tristate leakage current

IS_SOoff -10

–

µA

VS_SO = Vcc

P_11.3.8

Timings

Serial clock frequency

fS_CLK

0–

MHz CL= 50 pF 1)

P_11.3.9

Serial clock period

tS_CLK(P) 200

–

P_11.3.10

Serial clock high time

tSCLK(H) 50

–

P_11.3.11

Serial clock low time

tSCLK(L) 50

–

P_11.3.12

Enable lead time (falling CS to rising

SCLK)

tCS(lead) 250

–

P_11.3.13

Enable lag time (falling SCLK to rising

CS)

tCS(lag)

250

–

P_11.3.14

Transfer delay time (rising CS to

falling CS)

tCS(td)

250

–

P_11.3.15

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