ASL4501SHN datasheet(12/43 Pages) NXP

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ASL4501SHN

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Product data sheet

Rev. 2 — 10 January 2018

12 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

8.2.4 Enabling of connected phases

The gate driver enable register is used to configure which of the phases is active.

8.2.5 Boost converter frequencies configuration

The operation frequency of the boost converters can be set with via several SPI registers.

To ensure a stable phase delay between the different phases, all timings are derived from

the same oscillator. An integer number downscales the internal oscillator frequency for

each regulation loop. This slower clock is then used to control the off time of a phase. It

also controls the delay from one phase of the regulation loop to the next internal phase.

The number of phases determinates finally when the phase is turned on again and defines

so the operation frequency of the boost converter.

Table 9.

Gate driver enable (address 01h)

Bit

Symbol

Description

Value

Function

7 to 4

reserved

0000

reserved for future use: keep clear

EN_G4

phase 4 enabled

phase 4 is off

phase 4 is enabled

EN_G3

phase 3 enabled

phase 3 is off

phase 3 is enabled

EN_G2

phase 2 enabled

phase 2 is off

phase 2 is enabled

EN_G1

phase 1 enabled

phase 1 is off

phase 1 is enabled

Fig 6.

Phase control generator

aaa-017533

PHASE CONTROL GENERATOR

combined

reset

Ph0

PHASE

GATING

COUNTER

COUNTER (DIV N)

switching

frequency

phase delay and

phase off parameters

phase active

phase_gen_rst

rst_n

clk

config change

Ph1

Ph2

Ph3

slope comp clk

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