ASL4501SHN datasheet(18/43 Pages) NXP

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ASL4501SHN

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Product data sheet

Rev. 2 — 10 January 2018

18 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

8.6.1 Frequency trimming

It is mandatory to adjust the internal oscillator frequency of the device to ensure the

ASL4501SHN is operating within the specified oscillator frequency range.

To measure the actual internal frequency, the device measures the time that the CSB pin

is LOW during an SPI transfer. This time information is used to adjust the oscillator

frequency of the device. The recommended procedure for the time adjustment is shown in

Figure 7.

At the start of the sequence, the CSB LOW count feature is activated. It is done by setting

the Cnt_CSB bit HIGH in the frequency trimming control register (bit 3; register 00h). The

device now measures the time with its internal time domain each time the CSB pin is

LOW. It makes this information available in the CSB count registers. To allow an exact

stable reading, set the Cnt_CSB bit LOW again with an accurately known CSB LOW time.

Setting the bit LOW freezes the count registers. These registers store the last value,

which in this case is the command that sets the Cnt_CSB bit LOW.

The CSB count registers contain the count of the CSB LOW time of the last SPI command

the CSB LOW count feature was enabled. CSB count register 1 contains the bits 7 to 0 of

the counter, while the CSB count register 2 contains the bits 15 to 8.

Fig 7.

Frequency trimming flow

Table 25.

CSB count register 1 (address 41h)

Bit

Symbol

Description

Value

Function

7 to 0

CSB_cnt[7:0]

CSB count LOW

...

count value (bits 7 to 0)

aaa-017534

COUNT as

expected?

Frequency

trimming start

End frequency

trimming

yes

remark: count = CSB LOW TIME

(± 1 %)

fosc_trimmed

Enable CSB low

count feature

(CNT_CSB = 1)

Disable CSB low

count feature

(CNT_CSB = 0)

With defined, CSB

LOW TIME

Read CSB

count registers

Adjust frequency

trimming register

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