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USB333X bảng dữ liệu(PDF) 47 Page - Microchip Technology

tên linh kiện USB333X
Giải thích chi tiết về linh kiện  Industry?셲 Smallest Hi-Speed USB Transceiver with Single Supply Operation
PDF  85 Pages
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Trang chủ  http://www.microchip.com
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 2009 - 2015 Microchip Technology Inc.
DS00001880A-page 47
USB333x
Note 1:
An ‘X’ is a do not care and can be either a logic 0 or 1.
2:
The value of VbusValid is defined in Table 5-7.
6.3.1.1
Definition of Linestate
The Linestate information is used to relay information back to the Link on the current status of the USB data lines, DP
and DM. The definition of Linestate changes as the USB333x transitions between LS/FS mode, HS mode, and HS
Chirp.
6.3.1.1.1
LS/FS Linestate Definitions
In LS and FS operating modes the Linestate is defined by the outputs of the LS/FS Single Ended Receivers (SE RX).
The logic thresholds for single ended receivers, VILSE and VILSE are shown in Table 4-6.
Low Speed uses the same Linestate decoding threshold as Full Speed. Low Speed re-defines the Idle state as an inver-
sion of the Full Speed idle to account for the inversion which occurs in the hub repeater path. Linestates are decoded
exactly as in Table 6-4 with the idle as a K state.
6.3.1.1.2
HS Linestate Definition
In HS mode the data transmission is too fast for Linestate to be transmitted with each transition in the data packet. In
HS operation the Linestate is redefined to indicate activity on the USB interface. The Linestate will signal the assertion
and de-assertion of squelch in HS mode.
[5:4]
Rx Event
Encoding
ENCODED UTMI EVENT SIGNALS
VALUE
RXACTIVE
RXERROR
HOSTDISCONNECT
00
0
0
0
01
1
0
0
11
1
1
0
10
X
X
1
[6]
State of ID
pin
Set to the logic state of the ID pin. A logic low indicates an A device. A logic high
indicates a B device.
[7]
alt_int
Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event
occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit
Interrupt Latch register to determine the source of the interrupt. Section 5.6.1 describes
how a change on the ID pin can generate an interrupt. Section 6.8 describes how an
interrupt can be generated when the RidConversionDone bit is set.
TABLE 6-4:
USB LINESTATE DECODING IN FS AND LS MODE
Linestate[1:0]
DP SE RX
DM SE RX
State
00
SE0
0
0
USB Reset
01
J (FS idle)
1
0
J State
10
K (LS Idle)
0
1
K State
11
SE1
1
1
SE1
TABLE 6-5:
USB LINESTATE DECODING IN HS MODE
Linestate[1:0]
DP SE RX
DM SE RX
State
00
SE0
0
0
HS Squelch asserted
01
J
1
0
HS Squelch de-asserted
10
K
0
1
Invalid State
11
SE1
1
1
Invalid State
TABLE 6-3:
ULPI RX CMD ENCODING (CONTINUED)
Data[7:0]
Name
Description and Value



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