AM79C930 datasheet(49/161 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C930

TXDATA

2 X TSCLK

TGAP2 X TBCLK

+ 2 X TSCLK

TGAP1 X TBCLK

+ 2 X TSCLK

1st

Data Bit

Last

Data Bit

2 X TSCLK

TXS

4 X TSCLK

TSCLK = TCLKIN when

CLKGT20 = 0

TBCLK = TSCLK X 20

TGAP3 X TBCLK

+ 2 X TSCLK

O_TX

TXP_ON

3 X TSCLK

HDB X TBCLK

TX default bit

DRB X TBCLK

TGAP4 X TBCLK

+ 2 X TSCLK

TX default bit

7 X TSCLK

20183B-7

Figure 1. Transmitter Power Ramp Control

The values HDR, DRB, TGAP1, TGAP2, TGAP3, and

TGAP4 are programmable values that are stored in

TCR register locations TCR0, TCR5, and TCR6. All

other timings in the diagram are fixed with the values in-

dicated. The CLKGT20 control bit is located in MIR9[7].

The timing of the five internal signals can be applied to

the external pins

TXCMD, TXPE, and TXMOD in

either of two ways, depending upon the value pro-

grammed into the RCEN bit of TIR11 as shown in the

following table:

Timing Reference

Name

When RCEN=0

When RCEN=1

TXCMD

O_TX

TXPE

TXP_ON

TXMOD

Note that the TXCMD, TXPE, and TXMOD bits of TIR11

may also affect the values of the

TXCMD, TXPE, and

TXMOD pins. See the individual descriptions of these

pins in the

Multi-Function Pin section of this document

for more detail.

The polarity of

TXMOD and TXPE are programmable. A

separate TXCMD signal (inverse polarity to

TXCMD)

is available.

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