AM79C930 datasheet(23/161 Pages) AMD

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Am79C930

PRELIMINARY

ISA PLUG AND PLAY PIN SUMMARY

No. of

Pins

Pin Name

Pin Function

Pin Style

LA23–LA17

ISA upper address bus lines

SA16–SA0

ISA lower address bus lines

SD7–SD0

ISA data bus lines

TS2

RESET

RESET input

MEMR

Memory Read—used to enable the output drivers of the Am79C930 device for

ISA bus memory read accesses

MEMW

Memory Write—used to indicate that the current ISA bus cycle is a memory

write access

AEN

Address Enable—used to indicate that the current ISA bus I/O address is valid

BALE

Bus Address Latch Enable—used to indicate that the ISA address lines are

valid

IOCHRDY

I/O Channel Ready—used to delay the termination of the current ISA bus cycle

TS2

IOR

I/O Read—this signal is asserted by the ISA host system whenever an I/O read

operation occurs

IOW

I/O Write—this signal is asserted by the ISA host system whenever an I/O write

operation occurs

IRQ4, 5, 9, 10, 11, 12

Interrupt Request—this line is asserted when the Am79C930 device needs

servicing from the software

PTS3/OD2

RFRSH

Refresh—indicates that the current ISA bus cycle is a refresh operation

PCMCIA

PCMCIA mode—selects PCMCIA or ISA Plug and Play mode

PWRDWN

Powerdown—indicates that device is in the power down mode

TP1

MA16–0

Memory Address Bus—these lines are used to address locations in the Flash

device, the SRAM device, and an extra peripheral device that are contained

within an Am79C930-based design

TP1

MD7–0

Memory Data Bus—these lines are used to write and read data to/from Flash,

SRAM, and/or an extra peripheral device within an Am79C930-based design

TS1

FCE

Flash Chip Enable—this signal becomes asserted when the Flash device has

been addressed by either the 80188 core of the Am79C930 device or by the

software through the PCMCIA interface

TP1

SCE

SRAM Chip Enable—this signal becomes asserted when the SRAM device

has been addressed by either the 80188 core of the Am79C930 device or by

the software through the PCMCIA interface

TP1

XCE

eXtra Chip Enable—this signal becomes asserted when the extra peripheral

device has been addressed by the 80188 core of the Am79C930 device (XCE

is not accessible through the system interface)

TP1

MOE

Memory Output Enable—this signal becomes asserted during reads of devices

located on the memory interface bus

TP1

MWE

Memory Write Enable—this signal becomes asserted during writes to devices

located on the memory interface bus

TP1

TCK

Test Clock—this is the clock signal for IEEE 1149.1 testing

TDI

Test Data In—this is the data input signal for IEEE 1149.1 testing

TDO

Test Data Out—this is the data output signal for IEEE 1149.1 testing

TS1

TMS

Test Mode Select—this is the test mode select for IEEE 1149.1 testing

TRST

Test Reset—this is the reset signal for IEEE 1149.1 testing

TEST

Test pin—when asserted, this pin places the Am79C930 device into a

non-IEEE 1149.1 test mode

CLKIN

Clock input to drive BIU, 80188 core, and TAI, supplying network data rate

information

PMX1–2

Power Management Xtal—32-kHz Xtal input for sleep timer reference

I/XO

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