151

TM

March 1997

HM-6514/883

1024 x 4 CMOS RAM

Features

• This Circuit is Processed in Accordance to MIL-STD-

883 and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

• Low Power Standby. . . . . . . . . . . . . . . . . . . 125

µW Max

• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min

• TTL Compatible Input/Output

• Common Data Input/Output

• Three-State Output

• Standard JEDEC Pinout

• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max

• 18 Pin Package for High Density

• Gated Inputs - No Pull Up or Pull Down Resistors

Required

• On-Chip Address Register

Description

The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-

cated using self-aligned silicon gate technology. The device

utilizes synchronous circuitry to achieve high performance

and low power operation.

On chip latches are provided for addresses allowing efficient

interfacing with microprocessor systems. The data output

can be forced to a high impedance state for use in expanded

memory arrays.

Gated inputs allow lower operating current and also eliminates

the need for pull up or pull down resistors. The HM-6514/883 is

fully static RAM and may be maintained in any state for an

indefinite period of time.

Data retention supply voltage and supply current are guaran-

teed over temperature.

Ordering Information

Pinout

HM-6514/883

(CERDIP)

TOP VIEW

120ns

200ns

300ns

TEMPERATURE RANGE

PACKAGE

PKG. NO.

HM1-6514S/883

HM1-6514B/883

HM1-6514/883

CERDIP

F18.3

PIN

DESCRIPTION

A

Address Input

E

Chip Enable

W

Write Enable

D

Data Input

Q

Data Output

10

11

12

13

14

15

16

17

18

9

8

7

6

5

4

3

2

1

VCC

A8

A9

DQ0

DQ1

DQ2

DQ3

A7

W

A6

A5

A4

A3

A0

A1

E

A2

GND

FN2996.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Copyright © Intersil Americas Inc. 2002. All Rights Reserved