HM1-6514SSLASH883 datasheet(6/9 Pages) INTERSIL

6 / 9 page

156

Timing Waveforms

The address information is latched in the on-chip registers

on the falling edge of E (T = 0). Minimum address set up and

hold time requirements must be met. After the required hold

time, the addresses may change state without affecting

device operation. During time (T = 1) the output becomes

enabled but data is not valid until during time (T = 2). W must

remain high throughout the read cycle. After the output data

has been read, E may return high (T = 3). This will disable

the output buffer and all inputs, and ready the RAM for the

next memory cycle (T = 4).

(8)

(7) TAVEL

(6)

(4) TEHQZ

HIGH Z

VALID DATA OUT

(6)

HIGH Z

TAVEL

(7)

-1

TIME

REFERENCE

(2) TAVQV

(17) TELEL

TELAX

NEXT ADD

TEHEL

(2) TAVQY

TEHEL

(5) TELEH

(1) TELQV

(3) TELQX

FIGURE 1. READ CYCLE

VALID ADD

TRUTH TABLE

TIME

REFERENCE

INPUTS

DATA I/O

FUNCTION

-1

Memory Disabled

Cycle Begins, Addresses are Latched

Output Enabled

Output Valid

Read Accomplished

Prepare for Next Cycle (Same as -1)

Cycle Ends, Next Cycle Begins (Same as 0)

HM-6514/883

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