TMS320VC5506ZAYR datasheet(76/119 Pages) TI1

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Electrical Specifications

October 2006 − Revised January 2008

SPRS375C

5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of

N to generate the internal CPU clock cycle. The synthesis factor is determined by:

N= M

where: M = the multiply factor set in the PLL_MULT field of the clock mode register

DL = the divide factor set in the PLL_DIV field of the clock mode register

Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4.

For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview

Reference Guide (literature number SPRU317).

Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−4).

Table 5−4. Multiply-By-N Clock Option Timing Requirements

NO.

MIN

MAX

UNIT

tc(CI)

Cycle time, X2/CLKIN

DPLL synthesis enabled

20†

400

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

C11

tw(CIH)

Pulse duration, CLKIN high

† The clock frequency synthesis factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within

the specified range (tc(CO)). If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1.

Table 5−5. Multiply-By-N Clock Option Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

9.26

tc(CI)*N‡

1600

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H − 1

H + 1

tw(COH)

Pulse duration, CLKOUT high

H − 1

H + 1

C12

td(CI–CO) Delay time, X2/CLKIN high/low to CLKOUT high/low

‡ N = Clock frequency synthesis factor

C12

X2/CLKIN

CLKOUT

Bypass Mode

C10

C11

NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform

relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration.

Figure 5−4. External Multiply-by-N Clock Timings

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