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TMS320VC5506ZAYR bảng dữ liệu(PDF) 52 Page - Texas Instruments |
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TMS320VC5506ZAYR bảng dữ liệu(HTML) 52 Page - Texas Instruments |
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52 / 119 page  Functional Overview 52 October 2006 − Revised January 2008 SPRS375C Table 3−19. DMA Configuration Registers (Continued) PORT ADDRESS (WORD) RESET VALUE† DESCRIPTION REGISTER NAME CHANNEL #1 REGISTERS 0x0C20 DMA_CSDP1 DMA Channel 1 Source Destination Parameters Register 0000 0000 0000 0000 0x0C21 DMA_CCR1[15:0] DMA Channel 1 Control Register 0000 0000 0000 0000 0x0C22 DMA_CICR1[5:0] DMA Channel 1 Interrupt Control Register xxxx xxxx xx00 0011 0x0C23 DMA_CSR1[6:0] DMA Channel 1 Status Register xxxx xxxx xx00 0000 0x0C24 DMA_CSSA_L1 DMA Channel 1 Source Start Address Register (lower bits) Undefined 0x0C25 DMA_CSSA_U1 DMA Channel 1 Source Start Address Register (upper bits) Undefined 0x0C26 DMA_CDSA_L1 DMA Channel 1 Source Destination Address Register (lower bits) Undefined 0x0C27 DMA_CDSA_U1 DMA Channel 1 Source Destination Address Register (upper bits) Undefined 0x0C28 DMA_CEN1 DMA Channel 1 Element Number Register Undefined 0x0C29 DMA_CFN1 DMA Channel 1 Frame Number Register Undefined 0x0C2A DMA_CSFI1 DMA Channel 1 Source Frame Index Register Undefined 0x0C2B DMA_CSEI1 DMA Channel 1 Source Element Index Register Undefined 0x0C2C DMA_CSAC1 DMA Channel 1 Source Address Counter Undefined 0x0C2D DMA_CDAC1 DMA Channel 1 Destination Address Counter Undefined 0x0C2E DMA_CDEI1 DMA Channel 1 Destination Element Index Register Undefined 0x0C2F DMA_CDFI1 DMA Channel 1 Destination Frame Index Register Undefined CHANNEL #2 REGISTERS 0x0C40 DMA_CSDP2 DMA Channel 2 Source Destination Parameters Register 0000 0000 0000 0000 0x0C41 DMA_CCR2[15:0] DMA Channel 2 Control Register 0000 0000 0000 0000 0x0C42 DMA_CICR2[5:0] DMA Channel 2 Interrupt Control Register xxxx xxxx xx00 0011 0x0C43 DMA_CSR2[6:0] DMA Channel 2 Status Register xxxx xxxx xx00 0000 0x0C44 DMA_CSSA_L2 DMA Channel 2 Source Start Address Register (lower bits) Undefined 0x0C45 DMA_CSSA_U2 DMA Channel 2 Source Start Address Register (upper bits) Undefined 0x0C46 DMA_CDSA_L2 DMA Channel 2 Source Destination Address Register (lower bits) Undefined 0x0C47 DMA_CDSA_U2 DMA Channel 2 Source Destination Address Register (upper bits) Undefined 0x0C48 DMA_CEN2 DMA Channel 2 Element Number Register Undefined 0x0C49 DMA_CFN2 DMA Channel 2 Frame Number Register Undefined 0x0C4A DMA_CSFI2 DMA Channel 2 Source Frame Index Register Undefined 0x0C4B DMA_CSEI2 DMA Channel 2 Source Element Index Register Undefined 0x0C4C DMA_CSAC2 DMA Channel 2 Source Address Counter Undefined 0x0C4D DMA_CDAC2 DMA Channel 2 Destination Address Counter Undefined 0x0C4E DMA_CDEI2 DMA Channel 2 Destination Element Index Register Undefined 0x0C4F DMA_CDFI2 DMA Channel 2 Destination Frame Index Register Undefined † Hardware reset: x denotes a “don’t care.” |
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