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LMX9820ASM bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI) |
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LMX9820ASM bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI) |
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6 / 44 page ![]() www.national.com 6 Revision 1.0 5.0 Pad Descriptions (Continued) Table 5. Auxiliary Ports Interface Signals Pad Name Pad Location Direction Description IOVCC H12 Input 2.85V to 3.6V Logic Threshold Program Input. Reset_b# G8 Input Reset for Smart Radio. Connect to Reset_5100. Reset_5100# D11 Input Reset for Baseband processor. Low active, either connect to host or use pull-up with max. 1K Ω resistor. Lstat_0 E8 Output Link Status Bit 0 Lstat_1 F8 Output Link Status Bit 1 Host_wu F9 Output Host Wakeup Env0 E9 Input Module Operating Environment Bit 0 Env1 B11 Input Module Operating Environment Bit 1 TX_Switch_P H3 Output Transceiver Status. 0 = Receive; 1 = Transmit. Table 6. Audio Port Interface Signals Pad Name Pad Location Direction Description AAI_srd B10 Input Advanced Audio Interface Receive Data Input 1 AAI_std B12 Output Advanced Audio Interface Transmit Data Output 1 AAI_sfs C11 Input/Output Advanced Audio Interface Frame Synchronization 1 AAI_sclk C12 Input/Output Advanced Audio Interface Clock 1 1. Treat as no connect if not used. Pad required for mechanical stability. Table 7. Test Interface Signals Pad Name Pad Location Direction Description J_rdy E10 Output JTAG Ready 1 J_tdi F10 Input JTAG Test Data 1 J_tdo F11 Input/Output JTAG Test Data 1 J_tms G9 Input/Output JTAG Test Mode Select 1 J_tck G10 Input JTAG Test Clock 1 PI1_RFCE_TP11 A8 Test Pin Module Test Point 1 PI2_TP12 A13 Test Pin Module Test Point 1 Tx_rx_data C8 Test Pin Module Test Point 1 Tx_rx_synch A10 Test Pin Module Test Point 1 CCB_Clock A11 Test Pin Module Test Point 1 CCB_data D8 Test Pin Module Test Point 1 CCB_latch J12 Test Pin Module Test Point 1 BBCLK A12 Test Pin Module Test Point 1 PH3_TP9 F13 Test Pin Module Test Point 1 PH2_TP8 G13 Test Pin Module Test Point 1 |
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