MMA8652FC datasheet(10/65 Pages) NXP

10 / 65 page

MMA8652FC

Sensors

Freescale Semiconductor, Inc.

2.4

I2C interface characteristic

Figure 4. I2C slave timing diagram

Table 6. I2C slave timing values (1)

1. All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.

Parameter

Symbol

I2C Fast Mode

Unit

Min

Max

SCL clock frequency

fSCL

400

kHz

Bus-free time between STOP and START condition

tBUF

1.3

μs

(Repeated) START hold time

tHD;STA

0.6

μs

Repeated START setup time

tSU;STA

0.6

μs

STOP condition setup time

tSU;STO

0.6

μs

SDA data hold time

tHD;DAT

0.05

0.9 (2)

2. This device does not stretch the LOW period (tLOW) of the SCL signal.

μs

SDA setup time

tSU;DAT

100

SCL clock low time

tLOW

1.3

μs

SCL clock high time

tHIGH

0.6

μs

SDA and SCL rise time

20 + 0.1 Cb

(3)

3. Cb = total capacitance of one bus line in pF.

300

SDA and SCL fall time

20 + 0.1 Cb

(3)

300

SDA valid time (4)

4. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;DAT

0.9 (2)

μs

SDA valid acknowledge time (5)

5. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;ACK

0.9 (2)

μs

Pulse width of spikes on SDA and SCL that must be suppressed by

internal input filter

tSP

050

Capacitive load for each bus line

400

VIL = 0.3 VDD

VIH = 0.7 VDD

MMA8652FC bảng dữ liệu(PDF) 10 Page - NXP Semiconductors

MMA8652FC bảng dữ liệu(HTML) 10 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

bảng dữ liệu tải về

Link URL