PC8245 datasheet(2/61 Pages) ATMEL

2 / 61 page

PC8245

2171D–HIREL–06/04

General Description

Block Diagram

The PC8245 integrated processor is comprised of a peripheral logic block and a 32-bit

superscalar PowerPC 603e core, as shown in Figure 1.

Figure 1. Block Diagram

Peripheral Logic

Instruction Unit

Address

Translator

DLL

Fanout

Buffers

PCI

Arbiter

I2C

Controller

DMA

Controller

EPIC

Interrupt

Controller

/Timers

DUART

Watchpoint

Facility

PCI Bus

Interface Unit

Data Path

ECC Controller

Memory

Controller

Central

Control

Unit

Oscillator

Input

Five Request/

Grant Pairs

I2C

5 IRQs/

16 Serial

Interrupts

Processor Core Block

Peripheral Logic Block

Processor

PLL

Instruction

MMU

(64-bit) Two-instruction fetch

(64-bit) Two-instruction dispatch

Peripheral Logic

PLL

SDRAM Clocks

PCI_SYNC_IN

PCI Bus

Clocks

Data (64-bit)

Address

(32-bit)

Data Bus

(32- or 64-bit)

with 8-bit Parity

or ECC

Memory/ROM/PortX

Address and Control

64-bit

32-bit

PCI Interface

Branch

Processing

Unit

(BPU)

System

Unit

(SRU)

Floating

Point

Unit

(FPU)

Integer

Unit

(IU)

Load/Store

Unit

(LSU)

Bus

Performance

Monitor

Data

MMU

16-Kbyte

Data

Cache

16-Kbyte

Instruction

Cache

Configuration

Registers

Additional features:

• Prog I/O with Watchpoint

• JTAG/COP Interface

• Power Management

PC8245

SDRAM_SYNC_IN

Message

Unit

(with I2O)

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