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ST8500 bảng dữ liệu(PDF) 24 Page - STMicroelectronics

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ST8500 bảng dữ liệu(HTML) 24 Page - STMicroelectronics

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Pinout and pin description
ST8500
24/37
DocID031029 Rev 3
3.2
GPIOs multiplexing scheme
In the ST8500 device, peripherals are connected to I/Os through a multiplexer. At a given
time, each I/O can be controlled by only one single peripheral. In this way, there is no
conflict between peripherals sharing the same I/O pins.
Thanks to a set of configuration registers, the user can select one of the three possible
alternate functions for each pin as described in Table 8.
Table 8. GPIOs multiplexing scheme
Pin name
Selection: 11
Selection: 00
Selection: 01
Selection: 10
GPIO00_0
Input/output
USART1_RX
SPI2_SCLK
RESERVED
GPIO00_1
Input/output
USART1_TX
SPI2_MOSI
RESERVED
GPIO00_2
Input/output
USART1_RTS
SPI2_SSn
RESERVED
GPIO00_3
Input/output
USART1_CTS
SPI2_MISO
RESERVED
GPIO00_4
Input/output
USART0_RX
SPI0_SCLK
RESERVED
GPIO00_5
Input/output
USART0_TX
SPI0_MOSI
RESERVED
GPIO00_6
Input/output
USART0_RTS
SPI0_SSn
RESERVED
GPIO00_7
Input/output
USART0_CTS
SPI0_MISO
RESERVED
GPIO01_0
Input/output
SPI1_SCLK
-
RESERVED
GPIO01_1
Input/output
SPI1_MOSI
-
RESERVED
GPIO01_2
Input/output
SPI1_SSn
USART0_SCLK
RESERVED
GPIO01_3
Input/output
SPI1_MISO
-
RESERVED
GPIO01_4
Input/output
USART2_RX
I2C0_SMBA
RESERVED
GPIO01_5
Input/output
USART2_TX
USART1_SCLK
RESERVED
GPIO01_6
Input/output
USART2_RTS
I2C0_SDA
RESERVED
GPIO01_7
Input/output
USART2_CTS
I2C0_SCL
RESERVED
GPIO03_0
Input/output
BOOT0
-
RESERVED
GPIO03_1
Input/output
BOOT1
-
RESERVED
GPIO03_2
Input/output
BOOT2
-
RESERVED
GPIO03_3
Input/output
JTAG_TMS/SWIO
-
RESERVED
GPIO03_4
Input/output
JTAG_TCK/SWCLK
-
RESERVED
GPIO03_5
Input/output
JTAG_TDO/SWV
-
RESERVED
GPIO03_6
Input/output
JTAG_TRSTn
-
RESERVED
GPIO03_7
Input/output
JTAG_TDI
-
RESERVED



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