ST8500 datasheet(16/37 Pages) STMICROELECTRONICS

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Device architecture

ST8500

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DocID031029 Rev 3

The application code can select the clock source for the Cortex™-M4 subsystem between:

The VCO output of FS by means of a programmable pre-scaler. The application core

must properly configure it to provide the clock in the range from 1.5 MHz to 200 MHz.

The 25 MHz oscillator by means of a programmable pre-scaler at a nominal frequency

ranging from 0.8 MHz up to 25 MHz.

The internal ring oscillator, either directly (at a nominal frequency 4 MHz) or by means

of a fixed pre-scaler (at a nominal frequency of 0.125 MHz).

Each APB bus can be fed at an integer fraction of the Cortex™-M4F clock with a prescaling

factor up to 8. The application core must configure the APB clock to respect the maximum

limit of 100 MHz. USART and I2C peripherals have an independent clock divider to generate

the proper baudrate and clock on the line.

It is also possible to apply clock gating to each bus in case of low power mode or unused

peripherals. Clock gating can be applied to clock signals as indicated in Figure 3.

2.5.2

Reset management

The power-on-reset (POR) is conditioned by the level of the required supply voltages (3.3 V,

2.5 V and 1.1 V, see Section 2.6). At the power-on, the whole ST8500 is kept under reset

until the supply voltages are above the respective turn-on thresholds, while the device is

turned off as soon as one of the supply voltages fall below the respective turn-off thresholds.

The system reset is generated by:



The RESETn pin (active low)



The Cortex™-M4F core that can assert a system software reset



The window watchdog (see Section 2.2.8 on page 11)

The software reset to single peripherals can be forced through CRM registers.

2.6

Power management

The ST8500 shall be powered by at least two external supply voltages:



3.3 V for I/Os and TX driver



1.1 V for the digital part and memories

The device needs also an analog 2.5 V supply that can be either internally generated

through an LDO from the 3.3 V supply, or externally supplied.

The internal regulator connected to AVDD_2V5 is not designed to supply external circuitry;

its output is externally accessible for filtering the purpose only.

The only ground reference of the device is the exposed pad (EXPAD-GND). It has to be

properly soldered to a ground pad on the application PCB.

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