FXPS7115D4 datasheet(41/72 Pages) NXP

41 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

41 / 72

Table 60. I2C_ADDRESS - I2C slave address register (address 3Fh) bit allocation

Bit

Symbol

I2C_ADDRESS[7:0]

Factory Default (stored value)

Factory Default (read value)

Access

R/W

The default register value is 00h. If the register value is 00h, the I2C slave address is

60h and a value of 60h is transmitted in response to a read command. If the register is

written to a value other than 00h, the I2C slave address is the lower seven bits of the

actual register value and the actual register value is transmitted in response to a read

command.

7.7.12 DSP Configuration Registers (DSP_CFG_Ux)

The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the

DSP data path.

There are 5 DSP Configuration registers, however, only DSP_CFG_U1, DSP_CFG_U4

and DSP_CFG_U5 are used when the device is in SPI or I2C mode. The DSP_CFG_U2

and DSP_CFG_U3 registers are for factory use only and are used for internal tests.

7.7.12.1 Self-test control bits

The self-test control bits select one of the various analog and digital self-test features of

the device as shown in the table below. The self-test control bits are not included in the

read/write array error detection.

Table 61. Self-Test Control Bits (ST_CTRL[3:0])

ST_

CTRL[3]

ST_

CTRL[2]

ST_

CTRL[1]

ST_

CTRL[0]

Function

SNS_DATAx_X Contents (16-bit data)

Normal Pressure Signal

16-bit Absolute Pressure Data

P-Cell Common Mode Verification

16-bit Absolute Pressure Data

reserved

DSP write to SNS_DATAx_X registers inhibited.

0000h

DSP write to SNS_DATAx_X registers inhibited.

AAAAh

DSP write to SNS_DATAx_X registers inhibited.

5555h

DSP write to SNS_DATAx_X registers inhibited.

FFFFh

reserved

Digital Self-Test 0

Digital Self-Test Output

Digital Self-Test 1

Digital Self-Test Output

Digital Self-Test 2

Digital Self-Test Output

Digital Self-Test 3

Digital Self-Test Output

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