HX6228

2

FUNCTIONAL DIAGRAM

CE

NCS

NWE

NOE

MODE

DQ

H

L

H

L

Read

Data Out

H

L

L

X

Write

Data In

X

H

XX

XX

Deselected

High Z

L

X

XX

XX

Disabled

High Z

TRUTH TABLE

SIGNAL DEFINITIONS

A: 0-16

Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7

Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS

Not chip select, when at a low level allows normal operation. When at a high level NCS forces the SRAM to

a precharge condition, holds the data output drivers in a high impedance state and disables all the input

buffers except CE. If this signal is not used it must be connected to VSS.

NWE

Negative write enable, when at a low level activates a write operation and holds the data output drivers in

a high impedance state. When at a high level NWE allows normal read operation.

NOE

Negative output enable, when at a high level holds the data output drivers in a high impedance state. When

at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must

be connected to VSS.

CE

Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a

precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers

except the NCS input buffer. If this signal is not used it must be connected to VDD.

Notes:

X: VI=VIH or VIL

XX: VSS

≤VI≤VDD

NOE=H: High Z output state maintained

for NCS=X, CE=X, NWE=X

NCS

A:3-7,12,14-16

CE

NWE

NOE

WE • CS • CE

NWE • CS • CE • OE

Column Decoder

Data Input/Output

Row

Decoder

131,072 x 8

Memory

Array

A:0-2, 8-11, 13

#

Signal

All controls must be

enabled for a signal to

pass. (#: number of

buffers, default = 1)

1 = enabled

Signal

8

DQ:0-7

(0 = high Z)

•

•

•

•

•

•

8

8

9