MCP18480 datasheet(33/64 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

DS20091B-page 33

MCP18480

3.0

PIN DESCRIPTIONS

TABLE 3-1:

MCP18480 PIN DESCRIPTIONS

Pin Name

Number

Direction

Buffer

Type

Description

SSOP

VPOS

Positive supply input.

Internal Shunt Regulator connected between VPOS and VNEG limits the

potential to 12V between these two pins. A series resistor must be

placed on the VPOS pin to limit the current into the device.

OVTH

Overvoltage protection threshold.

An external resistor divider network is connected to this input pin to

program the overvoltage protection threshold. The selected external

resistor values for the OVTH to system ground and OVTH to VNEG resis-

tors should have currents in the 1 mA range. A typical Overvoltage

threshold is -76V. Internal hysteresis in the overvoltage input compar-

ator will allow proper operation once VNEG falls below the selected

threshold.

UVTH

Undervoltage lockout threshold.

An external resistor divider network is connected to this input pin to

program the undervoltage lockout threshold. If the voltage on UVTH is

less than VNEG + 2.5V, the undervoltage comparator will trip, indicating

an Undervoltage condition.

An external hysteresis resistor can be used to set the high-to-low

(VTHF) threshold below the low-to-high (VTHR) threshold. For telecom

network equipment, it is desirable to have shutdown occur at -38.5V

and the startup set at -43.0V.

UVHYS

Undervoltage internal comparator hysteresis.

An external resistor is connected between this input to the UVTH input

pin to adjust the hysteresis of the internal Undervoltage comparator.

Since it is desirable to shut down at -38.5V and restart at -43.0V in

telecom switch equipment.

UVD

I/O

Undervoltage event delay.

An external capacitor is connected to this input pin to set the delay

between when the UVTH pin drops below the trip point specified by the

voltage on the VREFIN pin and when the system shutdown occurs

(causing the PWRGOOD pin to be driven to an inactive level and the

GATE pin to be pulled to the VNEG pin voltage level). The UVD pin

sources a current equivalent to the IISET (in typical applications, the

IISET current equals 10 µA), which charges this external capacitor

while an internal comparator compares this voltage on the UVD pin to

|VREFIN|/2.

Typically, for telecom equipment, the system is expected to shut down

when the input voltage falls below -38.5V (±1.0V DC) for greater than

100 ms.

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

I = Input

O = Output

P = Power

CMOS = CMOS-compatible input

A = Analog

D = Digital

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