ST7FDALIF2M6 datasheet(67/141 Pages) STMICROELECTRONICS

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ST7DALI

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LITE TIMER (Cont’d)

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the I bit in the CC

to clear all pending interrupt bits before execut-

ing the HALT instruction. This avoids entering

other peripheral interrupt routines after executing

the external interrupt routine corresponding to

the wake-up event (reset or external interrupt).

11.3.4 Low Power Modes

11.3.5 Interrupts

Note: The TBxF and ICF interrupt events are con-

nected to separate interrupt vectors (see Inter-

rupts chapter).

They generate an interrupt if the enable bit is set in

the LTCSR1 or LTCSR2 register and the interrupt

mask in the CC register is reset (RIM instruction).

11.3.6 Register Description

LITE TIMER CONTROL/STATUS REGISTER 2

(LTCSR2)

Read / Write

Reset Value: 0x00 0000 (x0h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = TB2IE Timebase 2 Interrupt enable.

This bit is set and cleared by software.

0: Timebase (TB2) interrupt disabled

1: Timebase (TB2) interrupt enabled

Bit 0 = TB2F Timebase 2 Interrupt Flag.

This bit is set by hardware and cleared by software

reading the LTCSR register. Writing to this bit has

no effect.

0: No Counter 2 overflow

1: A Counter 2 overflow has occurred

LITE

TIMER

AUTORELOAD

(LTARR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = AR[7:0] Counter 2 Reload Value.

These bits register is read/write by software. The

LTARR value is automatically loaded into Counter

2 (LTCNTR) when an overflow occurs.

Mode

Description

SLOW

No effect on Lite timer

(this peripheral is driven directly

by fOSC/32)

WAIT

No effect on Lite timer

ACTIVE-HALT No effect on Lite timer

HALT

Lite timer stops counting

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Active

Halt

Exit

from

Halt

Timebase 1

Event

TB1F

TB1IE

Yes

Timebase 2

Event

TB2F

TB2IE

Yes

IC Event

ICF

ICIE

Yes

000

TB2IE

TB2F

AR7

AR3

AR2

AR1

AR0

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